1. Field of the Invention
The present invention relates to processors having embedded memories and more particularly to exposing and debugging defects within embedded memories of processors.
2. Description of the Related Art
Digital systems, such as microprocessors, include data paths, control paths and memories. Many known digital systems include embedded memories. One challenge associated with embedded memories relates to identifying defects within the embedded memory. Defects in memories may be due to shorts and opens in memory cells of the embedded memories, address decoder(s) and read/write logic. These defects may be modeled as Stuck-at Faults (SAF), Transition Faults (TF), Stuck Open Faults (SOF), Address Decoder Faults (AF), Coupling Faults (CF) and Neighborhood Pattern Sensitive Faults (NPSF) in the memory cells.
A plurality of classes of test algorithms have been proposed for detection of the memory faults. The plurality of classes of test algorithms includes deterministic test algorithms, pseudo random test algorithms and pseudo exhaustive test algorithms. A known deterministic test algorithm is a march test algorithm. A march test algorithm involves applying a finite sequence of march elements to each cell in the memory in either ascending or descending order before proceeding to the next memory cell. Different types of march tests used to detect faults in single-port memories and recently in multi-port memories have been proposed.
The memory test algorithms can be applied to the memory under test via memory testers. Testing via a memory tester involves providing a test bus from the input/output pins of the memory which is brought to the boundary of the integrated circuit in which the memory is embedded. Testing via a memory tester has known drawbacks including the wiring overhead of the test bus to access the memory under test and the cost of memory testers. Advantages of testing via a memory tester include the level of controllability and observability on the memory under test and the fact that the memory under test is tested at the speed that the I/O can allow it. To overcome the wiring overhead issue, serial-to-parallel interfaces have been included within an integrated circuit in which memory is embedded. Thus, the test bus is reduced in width; however, the delay for serial-to-parallel conversion becomes a bottleneck for at-speed memory test.
A typical high performance microprocessor has approximately 100 to 150 embedded memories. Considering the complexity of these devices and the fact that the Input/Output (I/O) connections of the microprocessors are much slower than their core clock rate, the external tester method is often an ineffective and inefficient method to test the memories embedded within large scale integrated circuits such as microprocessors.
A known method for testing embedded memories is by providing an embedded memory built in self test (MBIST) module to apply memory test patterns to the embedded memories. An MBIST module includes different components including a memory BIST controller. The memory BIST controller realizes the memory test algorithm. Known memory BIST controllers have been designed as Finite State Machine (FSM) based controllers or as microcode-based controllers. The FSM based memory BIST controller is efficient but lacks the flexibility necessary to accommodate changes in a memory test algorithm. The ability to change the memory test algorithm is desirable for devices fabricated using new technologies as well as for debugging a field return part. Microcode-based controllers are flexible and can apply different test algorithms. However, the efficiency and effectiveness of a microcode based controller depends on the architecture of the controller.
Regardless of the capabilities of the memory BIST module, it is desirable for the memory BIST module to be activated and for the test algorithm to be customized in different levels of test, e.g., manufacturing-level, board-level and system-level test. This implies that the memory BIST module should be able to communicate with different interfaces using different protocols. Furthermore, the status of the test should be made available and should be readily extractable.
One known method for memory diagnostics using a memory BIST module includes the use of an external error pin. The external pin method is a two-pass process. In the first pass, the memory BIST is executed on the memory under test and the output of a comparator is observed by an external tester via a dedicated external error pin. Every time a mismatch between the actual and expected data from the memory under test is detected, an error signal is asserted on an external error pin for one cycle. The external tester providing the reference clock to the chip records the cycle number that that the error signal is asserted on the external error pin. Once the memory BIST completes the testing of the memory under test, the erroneous row in the memory is computed by knowing the test algorithm and the pipe stage delay between the time a read has occurred until the external error pin is asserted. A full bit map of the memory error locations requires knowing the failing columns as well as the failing rows. Accordingly, in another pass, to find the failing column, the memory BIST is restarted and stopped at each failing cycle number. At each failing cycle number, the test is paused and then the output of the memory is read via, e.g., a scan shift, a RAM test interface, or some other method.
A disadvantage of the external error pin method is that the memory BIST is executed with the same frequency as the reference clock and thus the diagnostic is slowed down. Also, a method to read the contents of the memory in the second pass must be designed. The external pin method also presents a high run time as well as dependency on a special tester that can monitor the external error pin and save the clock number.
Accordingly, it is desirable to provide a memory BIST methodology that can run at speed, provide a simple extraction of the failed column data, provide a fast run time and can execute on any tester.